Static timing analysis (STA) can determine if there exist paths in an electrical circuit design with delays that exceed a given timing threshold. Such paths are commonly known as critical paths (CPs). When such a critical path is identified, the portion of the design associated with the critical path may need to be modified to satisfy the required timing thresholds. It is generally not preferred to make such design modifications if they can be avoided, since each such modification consumes time and system resources, as well as possibly introducing less optimal component configurations and sizes.
Modern designs generally consist of multiple sub-designs with varying functionality and may operate at different clock frequencies. The timing threshold for critical paths varies according to the clock frequency of the sub-design under consideration. Since STA generally considers all paths in an electrical circuit, a set of constraints (also called a mode or a design mode) may be applied to a design such that only sub-designs with a desired timing threshold or functionality are considered for analysis while other sub-designs are not considered or hidden from analysis. The set of constraints for each sub-design are typically created manually and require an independent STA run for each mode or set of constraints to ensure that the entire design is “covered” by STA and all critical paths have been identified.
However, mismanagement of the sets of constraints and corresponding STA runs could cause less than 100% STA coverage resulting in undetected critical paths. Since the number design modes or sets of constraints can exceed, for example, 32 in a modern design, a significant amount of time and system resources may need to be expended to ensure 100% STA coverage such that all critical paths have been identified.
Therefore, it is important to verify complete STA coverage by accurately identifying that all sub-designs have been considered by STA such that all critical paths have been considered.
Most approaches have focused on manual STA coverage analysis of the sets of constraints and corresponding STA runs to ensure that no critical paths have been missed. The typical design flow can involve a large number of static timing analysis (STA) runs in an iterative process. Each time the design is optimized via synthesis, floor planning, place and route, in-place optimization, and/or back annotated post layout, static timing analysis can be performed. The number of STA runs increase for each mode that is considered and increases the effort to verify complete STA coverage.
In a modern design there may be several modes, for example, one or more test modes and multiple functional modes. Typically, the constraints for each mode are created and analyzed manually Generation of constraints for each mode and subsequent STA analysis for a typical design can take several weeks to several months and is very error prone and complete coverage is not easy to determine.
For example, very often, incremental changes can be made to a design. Incremental design changes can imply that from one static timing run to the next, many of the same constraints still apply. However, design changes may cause some of the constraints to become invalid. The constraints that are manually generated initially might not be re-verified when incremental changes are made to the design. The constraints that are no longer valid (invalid constraints) can cause incomplete STA coverage and a bad design to be implemented.
Coverage analysis has been investigated within the context of individual STA runs or for localized design regions. For example, some static timing tools detect paths that are logically never used with Automated test Pattern Generation (ATPG) techniques; however, these techniques have been limited to a single set of constraints or single mode of operation without consideration of additional constraints or modes that can be imposed by independent STA runs. Moreover, current tools do not provide an automated mechanism to analyze global coverage across several independent STA runs. The problems of identifying global coverage can often involve human intervention. This human intervention can be required because the coverage reported for each STA run can be reported without consideration of multiple STA runs that are required to implement a modern design. Identification of global coverage is often managed manually and can require extensive communication between the engineer that performs the static timing analysis and designers that understand the architecture of the design. The manual analysis of the global coverage analysis can be quite time consuming and error prone, adding weeks to months in the design process. Errors in the static timing analysis could lead to the manufacture of a bad design.
To illustrate this, consider an example coverage analysis problem when static timing is used to analyze a circuit and when it is desired to determine if the analysis has actually covered the whole design. In this example, assume that a design is considered which operates in two modes, test mode and functional mode. When analyzing the timing for the functional mode, the test logic will be turned off so that the test enable will be “off” or “disabled” and the static timing tool will only see the logic or the path in which the circuit path corresponds to the functional mode. When a designer finishes performing a set of timing, the designer is satisfied that he has performed functional mode coverage. Next, the designer will run another static timing run and will turn on the test mode and disable the functional mode to look at all the path and circuit connections in test mode. Now, if this is the only constraint that has changed, then the designer has performed two completely separate static timing analysis runs and if the designer has in fact switched the “test bit” from a zero to a one, then it can be assumed that the whole design has been covered.
However, in practice, designers today are running a large number of different modes. After running many different static timing runs, a designer could have made a mistake in determining whether any portion of the design has or has not been covered, e.g., that when the designer copied and modified files for the timing analysis runs, designers could have mistakenly cut and pasted exactly the same thing and run two static timing run on exactly the same circuit and missed the timing of another part of the circuit.
Today, there are no known approaches for addressing this problem, which can for example, go through and consider all the independent static timing analysis runs, grab all the setup files and then perform analysis to make sure that the entire chip properly undergoes timing analysis. If it cannot be ensured that entire chip design has undergone timing analysis, then there might exist a slow path that was not discovered, which could result in an IC chip that is not functional.
Embodiments of the present invention provide a method and system for performing automatic STA coverage analysis while existing constraints can be automatically verified and/or automatically regenerated to ensure complete STA coverage. Using some embodiments of the present invention, STA coverage can be automatically verified while existing constraints can be automatically verified and/or automatically regenerated, ensuring complete STA coverage as well as accurate and efficient design implementation.
Further details of aspects, objects, and advantages of the invention are described below in the detailed description, drawings, and claims. Both the foregoing general description and the following detailed description are exemplary and explanatory, and are not intended to be limiting as to the scope of the invention.